1. Technical Field of the Invention
The embodiments of the invention relate to timing circuits and, more particularly, to a timing interface module to interface two different clock domains.
2. Description of Related Art
Electronic devices may employ various communication technologies to communicate. Communication links may be physical media and/or wireless links. Various communication links are known to interface at a chip level, board level, network level or at a much larger system level. Examples of communication links include buses within a digital processing device, such as a computer. Such examples include PCI (peripheral component interface) bus, ISA (industry standard architecture) bus, USB (universal serial bus), as well as other connecting media. Communication technologies are typically based on certain communicating protocols, such as SPI (system packet interface) and hypertransport (HT) based technologies. HT was also previously known as lightning data transport (LDT). The HT standard sets forth definitions for a high-speed, low-latency protocol that may interface with today's buses, such as AGP, PCI, SPI, 1394, USB2.0, and 1 Gbit Ethernet, as well as next generation buses including AGP8x, infiniband, PCI-X, PCI 3.0, and 10 Gbit Ethernet. HT interconnects provide high-speed data links between coupled devices and most HT enabled devices include at least a pair of HT ports so that HT enabled devices may be daisy-chained. In an HT chain or fabric, a device may communicate with other coupled devices using appropriate addressing and control. Examples of devices that may be HT chained include packet data routers, server computers, data storage devices, and other computer peripheral devices. In today's networks and/or systems employing a communication link for data transfer, it is common to see HT and/or SPI (such as SPI-4) protocols being employed.
In order to facilitate data transfer between devices (or circuits within a device), proper timing control between the two devices/circuits is a factor for consideration. Whenever there are more than one clock domain involved for the data transfer, a timing relationship between the two clock domains may need to be addressed, whether the system is asynchronous, synchronous or plesiochronous, or a variant of one of these.
For example, within an integrated circuit (IC) chip, various clock domains may exist. The different clock domains either operate from different clock sources or operate from the same clock source, but have different clock frequencies. Thus, a processor, a bus, memory controller, and I/O interfaces within a chip may operate at different frequencies, whether the clock signals for those domains are sourced from the same clock source or from different clock sources. With advanced processing systems that are manufactured as a single IC, the various functional units of the IC may operate at different frequencies, even though the clocks for the separate domains originate from a central clocking source, such as a phase locked loop (PLL) clocking source.
Whenever there are two domains operating at two different clocking frequencies, the data transfer between the two domains occur with some adjustment for the difference in the frequency, in order for a valid data transfer from one domain to the other may be achieved. In these instances, one domain will be operating at a faster frequency than the second domain so that the data transfer from the faster clock domain to the slower clock domain (or from the slower clock domain to the faster clock domain) should ensure that the two domains compensate for the difference in the clock frequency, so that data is not lost.
Generally, for many devices the relationship of the clocking frequency between the various domains is an integer multiple. That is, in many instances there is a base clock frequency and the remaining clock signals that are generated for the other domains are an integral multiple of the base clock frequency. If the base frequency is divided, the divisor is typically limited to 2, so that the fractional clock frequency is ½ the base clock frequency. Where the frequency difference of the two clock domains is an integer multiple of one another, the timing adjustment is fairly simple to implement. However, when the timing difference has a ratio other than integer multiple or a division of 2, the timing difference imposes greater complexity. When other than simple ratios are implemented, such as a ratio of 5:4, specialized circuitry may be employed within each domain to adjust for the difference in the timing of the two domains. This specialized logic typically is ratio-specific to the particular ratio of the difference of the two clock frequencies.
Whenever there are a number of domains operating at different clock frequencies, separate ratio specific logic may be employed within each domain. A link between two domains of different clock frequencies generally uses ratio-specific logic at each end. Where there are a number of cross-domain data transfers in which the domains are operating at different clock frequencies, the number of such ratio-specific logic may add significant complexity and occupy more than an insubstantial real state on the chip. Furthermore, each pair of ratio-specific logic between clock domains may add further complexity to the design of circuitry for cross-domain data transfer.
Accordingly, it would be advantageous to have a more flexible interface to obtain effective data transfers between two domains having different clock frequencies.